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Z-RAM

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Project Owner : PATHA SRILATHA
Created Date : Sun, 06/11/2011 - 16:04
Project Description :
ZRAM OVERHAULS DRAM Abstract- The zero-capacitor (Z-RAM) floating body memory is a dynamic memory built on an SOI substrate. It differs from a DRAM cell in that it does not rely on an external capacitor to store charge and reading is done by sensing cell current. The Z-RAM memory cell stores charge in its floating body and uses this charge to alter the threshold voltage and gain of the cell transistor. The advantages of the Z-RAM cell are numerous and include a smaller cell size, lithographic friendly processing, fast access time, it does not require any new materials or extra processing steps in the fabrication process and no additional processing steps for use as an embedded memory . Index terms:-zero capacitor RAM, floating body effect, SOI (silicon-on-insulator), transistor bit cell, silicon wafer, memory density, three dimensional packing. NOMENCLATURE:- 1) INTRODUCTION 2) TRANSISTOR USED TO STORE MEMORY 3) IMPORTANCE OF SOI WAFERS AND IT’S DEVIATION FROM ORDINARY SILICON WAFER 4) Z-RAM IN MICRO PROCESSOR 5) STORE AND READ PROCESS IN Z-RAM 6) SPEED AND RETENTION OF MEMORY 7) OVERCOMING THE ILLS IN Z-RAM 8) CONCLUSION 9) REFERENCES I .INTRODUCTION Z-RAM, short for "zero capacitor RAM", developed based on the floating body effect of silicon on insulator (SOI) process technology. The technology offers memory access speeds similar to the standard six-transistor SRAM cell used in cache memory but uses only a single transistor, therefore affording much higher packing densities. The beauty of Z-RAM: - No exotic semiconductors, no oddly structured parts, and no experimental insulators. Each memory cell is just a single transistor. That’s it. For comparison, conventional on-chip memories typically use six transistors per memory cell. So you can fit as much as 5 megabytes of Z-RAM into the space occupied by a single megabyte of conventional embedded memory. That lets you greatly increase the amount of memory on the chip and thereby improve its performance, make the chip a lot smaller and cheaper, or do a good deal of both II. TRANSISTOR USED TO STORE MEMORY The transistor is the most studied device in the To make it work as a memory, we had to find something different.” What they found was a way to temporarily store a bit as charge inside the body of a transistor made on a silicon-on-insulator (SOI) semiconductor wafer. Such wafers are gaining ground as the substrate for high-performance processors, such as the Cell microprocessor and Advanced Micro Devices’ this type of memory, termed a floating-body cell. III. IMPORTANCE OF SOI WAFERS AND IT’S DEVIATION FROM ORDINARY SILICON WAFER An SOI wafer differs from an ordinary silicon wafer in that it has a very thin layer of insulating silicon dioxide buried a few hundred nanometers or less below the surface. That layer of insulation cuts the transistor off from the vast bulk of the wafer—which, in turn, limits the amount of charge the transistor must move in order to switch on or off. As transistors shrink, they increasingly leak current, even when they are turned off. But the insulation in SOI wafers blocks a major pathway for that current, thus reducing the power that transistors draw by 30 ¬percent when they’re switching and 50 percent to 90 percent when they’re not. The SOI wafer lets you substitute Z-RAM for the chip’s conventional embedded memory. SOI’s insulating layer is key to storing the bit in Z-RAM, so you cannot build it on a plain wafer. By Innovative Silicon’s estimates, if the conventional memory takes up half the area, replacing it with Z-RAM would let designers shrink a chip to 72 square milli¬meters from 120 mm2. That would boost the number of chips per wafer and cut the final cost of the chip almost in half. IV. Z-RAM IN MICRO PROCESSORS Whether they're using SOI or not, microprocessor makers are compelled to continue boosting the amount of on-chip memory in their designs for the simple reason that they can’t get the performance they need any other way. The other means of increasing processing rates—running clocks at higher speeds and putting more processor cores on a chip—are effective only if those processor cores have rapid access to data. The standard form of embedded memory used on microprocessor chips is static random access memory. Designers incorporate the SRAM as blocks of memory called caches. The level 1 cache, or L1, is optimized for speed and located near the processor core on the chip. It stores the most frequently needed few kilobytes of data, so when the processor needs data, it looks there first. Then it checks in a larger but more distant and somewhat slower cache, called L2, which is usually about 16 MB these days but could balloon to 200 MB for next-generation chips. If the data it requires are in neither of those caches, on some processors there is a still larger cache, L3, in which to look. Failing that, it’s off to the computer’s main memory, which consists of hundreds of megabytes of dynamic random access memory (DRAM), or as a last resort, the HD. . But going off chip is costly, both in the amount of time the processor spends spinning its wheels waiting for data and in the power expended exporting data across the computer’s wiring. The performance boost you can get out of packing more memory into the CPU depends on the type of processor. V.STORE & READ PROCESS IN Z-RAM Z-RAM doesn’t just have to be better than traditional embedded SRAM; it also has to be better than DRAM, a memory technology that has been slowly winning a place on logic chips. Though slower than SRAM, DRAM consumes about one-fifth as much power and is about four times as dense. DRAM is so much denser than SRAM because it consists of a single transistor and a capacitor instead of SRAM’s six transistors. But that capacitor is the problem. Moore’s Law doesn’t apply to it, so it stays big while the transistors all around it continue their mad descent into the infinitesimal. The capacitor can’t shrink because it must stay large enough to store a detectable amount of charge. The growing mismatch between the size of transistors and the size of capacitors has led to strange-looking arrangements, such as capacitors built as narrow trenches having a depth many times greater than the chips’ transistors. Another configuration has relatively enormous fin-shaped capacitors built above the silicon in the area that usually holds the chip’s ¬wiring. Both arrangements are too expensive to put into many logic chips, requiring several extra manufacturing steps. Nevertheless, DRAM is a well-understood technology, and it is embedded in some memory-intensive chips such as IBM’s Blue Gene processor. Add the speed of SRAM to DRAM and remove the capacitor and you get Z-RAM. We can remove the capacitor in DRAM by turning a bug into a feature. The bug is typically called the ”floating-body effect.” The term comes from the fact that the insulation layer in an SOI wafer electrically separates the body of the transistors from the rest of the silicon, letting its voltage vary, or ”float.” The result can be a slight difference in the way transistors built in SOI operate from those fabricated in bulk silicon. In particular, it can lead to the transistor’s passing more current or less current for a given voltage signal, depending on how much current flowed in the recent past. When a transistor is ”on,” electric current runs from the transistor’s source to its drain. By the time those accelerating electrons get to the boundary of the drain, they are moving so quickly that some will whack into silicon atoms energetically enough to ionize them. This impact ionization, as it’s called, generates pairs of electrons and holes. The electrons exit the transistor through the drain, which is connected to a positive voltage. But the holes are repelled by the drain. In a bulk silicon crystal, this extra positive charge would harmlessly drift out into the silicon, but in SOI, the insulating layer traps it in the transistor, forming a body of charge that floats above the insulator. That floating charge, a minor annoyance to advanced processor designers, could be a wonderful thing. You can use it to store data—in fact, a transistor with such a floating charge is basically a Z-RAM cell storing a 1 To erase the 1 and store a 0, increase the voltage on the transistor’s gate. That pushes the holes out of the transistor through the source electrode and even leaves a slight negative charge behind. Reading a bit from a Z-RAM cell is simple. All you need to do is turn the transistor on and measure the amount of current flowing through it. For a field-effect transistor like the ones you’d find in a typical processor, turning the device on involves applying a voltage to the transistor’s gate. The voltage forces open a conductive channel between the source and the drain, allowing current to flow. More current will flow through a cell with a 1 than through one with a 0, because the floating body charge that makes up the bit exerts its own force on the channel and acts almost like a second gate, amplifying the effect of the real gate. If you compare the current of the memory cell to that of a reference cell, you can tell a 1 from a 0. VI. SPEED AND RETENTION OF MEMORY The difference between a 1 and 0 was just 3 micro amps, or 15 micro amps per micrometer of channel. Then, using the same transistor but a different set of input voltages The 1 signal can be made a sharp rectangle that was at least 10 times the size of either previous signal. ”It’s basically digital” Because the difference between the two states, the margin, is so enormous, there’s no need for the reference cells previous one required to interpret 1s and 0s. The much larger margin also means a cell can be read about twice as fast as a previous cell. What’s more, it uses considerably less power—75 percent less to read and 90 percent less to write. Part of the power savings comes because these cells hold their data longer. Z-RAM is similar to DRAM in that over a period of time the cell will inevitably lose its data. That is, 1 and 0 will become indistinguishable. For that reason, an array of Z-RAM must periodically be refreshed by reading and rewriting the data, a subtle but persistent drain on power. But Z-RAM requires fewer refreshes, because it takes about 8 seconds to lose its bit, and that’s 10 times as long as DRAM takes. . A Z-RAM array can be made to access data at 400 megahertz or more—about 60 percent faster than a comparable embedded DRAM array but still not as speedy as the fastest SRAM. Or it can be designed to draw a remarkably low 10 microwatts per megahertz—about 10 percent of comparable embedded DRAM. VII. OVERCOMING THE ILLS IN Z-RAM The reduced cell size leads, in a roundabout way, to Z-RAM being faster than even SRAM if used in large enough blocks. While individual SRAM cells are sensed faster than Z-RAM cells. So Z-RAM in bulk makes the difference, increasing the number of cell in Z-RAM can be done by fabricating the transistor bit cells horizontally. If three-dimensional packing is used where a chip with two or more layers of active electronic components, integrated both vertically and horizontally into a single circuit reduced the size of Z-RAM further smaller and reduces the physical distance between the memory blocks. Editor's Note: 1. Name: P.SRI LATHA College: SRITW, Anthasagar, Warangal, 3rd¬¬ year, CSE. . CONCLUSION Z-RAM offers the hope of cheaper on-chip memory, with little or no performance degradation, a compelling proposition if the memory cell can be proven to work in production volumes. If Z-RAM grabs even a little piece of the on-chip memory market, it will change the ground rules for microprocessor design. By the above paper, we can conclude the below points 1) Z-RAM gives a new ray for the chip industry by making large memory available with lower operating voltages and faster operation. 2) Implementation 3D packing technique in fabrication of Z-RAM can bring much more advancements. References:- 1) www.ieeespecrum.com 2) www.semiconductors.com
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