VLSI and WSI associative string processors for structured data processing

A novel fine-grain parallel-processing microelectronic architecture is proposed as a cost-effective building-block for fifth-generation computer systems. Based on a fully programmable associative string processing computational structure, the architecture provides particularly flexible support and manipulation of abstract data structures over a wide range of information processing tasks. Moreover, the architecture is well suited to the technological constraints of VLSI chip and, especially, WSI device fabrication. The paper describes the ASP (associative string processor) architecture and its instruction set. The style of associative string processing is introduced with three algorithms, illustrating both relational and arithmetic operations. Current projects leading to VLSI ASP chips and WSI ASP devices are discussed and 'ball-park' performance figures are given.


1 Introduction
Progress in the new fields of VLSI chip architecture, VLSI design methodology and VLSI design tools has led to the
design of increasingly complex microelectronic systems.Inevitably, 32-bit microprocessors and 256K dynamic
RAMs have figured prominently among such VLSI chipdesigns. Indeed, VLSI chip architectures, involving such
memory and processing logic on the same chip, have also been proposed. However, VLSI and more recently WSI
(wafer scale integration) are creating the opportunity for the integration of radically new parallel-processing computer
architectures. In addition to this technology push there are clear signsof a complementary systems pull for the development of  parallel-processing hardware. Indeed, the rapidly expanding field of information technology abounds with applications for such computational power in fifth-generation computer systems supporting image and speech processing, word and file processing, intelligent knowledgebase management and high-resolution graphics processing. This paper describes a particular contribution to current research leading towards the development of lowcost high-speed VLSI and WSI parallel-processing device architectures [1].

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