VHDL-A: a future standard for analog and mixed digital-analog description and simulation

VHDL is an IEEE standard language for the description and the simulation of digital circuits and systems. It is now experiencing a wider application domain as it may also be used for synthesis, formal verification and testing. Another natural evolution of VHDL is the capability to handle analog circuits and systems as well, and, as a direct consequence, mixed digital-analog circuits and systems. This paper describes the main aspects of such an evolution, called VHDL-A. It is a superset of VHDL under development within the IEEE. More generally, VHDL-A is intended to become a standard for the description and the simulation of continuous-time systems, which also include nonelectrical systems such as mechanical or thermal systems, and control systems

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