An undergraduate full-custom CMOS VLSI design course: CAD tools, fabrication, at MOSIS, and project examples

"BuckneN University has developed a senior-design course
using a combination of CAD tool famili&dion, and
presentations on specific and group topics that are critical to
various aspects of IC design Students complete a full-custom
CMOS VLSX design and in some cases submit their design for
fabrication at MOSIS.
Nationally, undergraduate electrical engineering cumcula
are under review for their design content. This review is driven
both b the Accreditation Board for Engineering Technology
(AsEl$ reviews, which are emphatic in their demands for
significant design content in the cumcula, and by industry, which
has been disappointed with the problem-solving slulls and
creativity of current electrical engineering aduates. Design,
however, is a difficult concept to define. A Erge portion of the
national debate on design in electrical engineerin cumcula
focuses on the definition of design. Emerging kom these
discussions is a consensus that design components of the
cumculum must present open-ended problems which offer
alternative solutions or approaches.
When faced with typical class sizes, open-ended design
problems, with their multiple solutions, present a significant
challenge for engineering faculty to evaluate. Students too, are
faced with a dilemma. For the student, aside from resortin to
construction of the project, which is time consuming and often
does not provide substantial insight into the design process,
computer-based simulation and analysis tools must be used to
assess their design. Unfortunately, in many areas of electrical
engineering, either the computer-based analysis and design tools
are too rudimentary, computational time excessive, or software
costs exceeds the University's means. Fortunately in the area of
VLSI, industry and academia have devoted considerable time
and expense to the development of accurate, effective, and
realistic computer-based design and analysis tools. Bucknell
University has developed a senior-design course which uses
some of these tools for CMOS VLSI design.
1. Course Overview
course for electrical engineering stufents. Students enter t E
VLSI course following a two-course electronics se uence;
students complete a full-custom CMOS VLSI design by %e end
of the semester-long VLSI course. During the initial
approximately six weeks of the VLSI course, students are
familiarized with the CAD tools through several shorter design
projects. T ically, these initial projects are one or two weeks in
duration. Yrojects assigned durinbthis familiarization phase
have included: optimum sizing of C OS inverters for mimmum
ro agation delay; a maximum density, 400fix400p one-bit
KO&; a 2-bit parallel multiplier; and an expandable 4-bit
arithmetic logic unit. The results from these projects vary widely
in quality. For instance, using 3-K technology, within a
4 0 0 x~ 4 00p total area, sizes of the one-bit ROM designs have
ranged from 16 bits upwards to 256 bits inclusive of the row and
column decoders.
Throughout these shorter projects, students gain
familiarity with the graphical layout tools, design-rule checking,
simulation modes and command files, and the concept of
hierarchical desi n Lectures during this period cover
conventional Vl.8 topics such as transistor sizing, rise-time and
fall-time predictions, PLAs, prechar e/evaluate logic, power
dissipation, transmmion gates, 8MOS fabrication and
processing, calculation of parasitic capacitances and resistances,
latchup, charge sharing, and CMOS design rules.
Bucknell University has develo ed a CMOS VLSI desi
Students are quick to appreciate the graphical interface
of the layout tools as well as the capabilities of a networked
workstation computing environment. Students are strongly
encouraged to take advantage of electronic mail (E-mail).
Questions and res onses are posted via E-mail and all designs
must be submittefvia E-mail. Students typically become very
comfortable with E-mail and use it extensively to communicate
with each other as well as with the instructor. All designs are
submitted electronically and grades and comments returned to
students electronically. It is essential that those students who
wish to submit their designs for fabrication at MOSIS [l] become
adept with the use of E-mail since all communication with
MOSIS is via E-mail.
Each individual student makes an informal, oral
presentation at the conclusion of every short project. Students
?re expected to offer criticisms and suggestions for
improvement, in addition querying design choices and
alternatives. Through these shorter design projects and
presentations, students realize that design alternatives are always
available and that these alternatives warrant consideration in the
design process.
At the conclusion of the six-week period, students have
identified a roject for the remainder of the course. In each
week throu&out the remainder of the course, each student is
required to present an oral report on a specific topic. These
topics alternate between a common topic assigned to every
student for that week, to specific topics judged critical to the
success of the student project. Common topics assigned to every
student include: design partitioning, floorplanning, transistor and
power budget, roject economics, testing, and projections of
design time. &embers of the class are cast as company
executives and serve as a review panel durin these
presentations. Suggestions and re uirements (deliverahes) for
subsequent presentations are proviled by class members. These
presentations force students to reckon with design critiques and
challenges, and to candidly defend their design choices.

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