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A test machine for digital VLSI circuits fabricated through MOSIS.

ABSTRACT - The design, construction, and operation of a PC based test machine is described which is used to test
digital VLSI devices fabricated throu,gh MOSIS. This test machine is capable of detecting gate and transistor level,
single and multiple stuck-at faults. The test machine was developed as a senior design project in electrical engineering
to provide students with experience in team based design of complete systems as well as the fundamental concepts of
manufacture testing and diagnosis of VLSI and digital systems.
1. INTRODUCTION
With the growing complexity of Very Large Scale Integrated (VLSI) circuits, the need for considering testing
issues at the very early stages of design is imperative. This paper describes a VLSI test machine that was designed and
constructed as a part of a senior capstone design course in the Department of Electrical Engineering at the University of
Kentucky. The intent of the course was two fold. The first goal was to emphasize the engineering design process while
facilitating the creative involvement of the students, as a team, in open-ended problems relating to actual designs that
are appropriate to the profession of electrical engineering. As a result, the students involved in the project gained
experience in the team based approach to designing and constructing a complete system (both hardware and software)
via design and development methodologies typically used in industry. In addition, emphasis was placed on the
manufacturing, production, and end use of the system. The second goal of the course and project was to introduce
students to the fundamental concepts of VLSI and digital system manufacturing testing and diagnosis. As a result,
students would consider testing and design for testability as part of the design process as opposed to a step at the backend of the development cycle. In addition, the students would have a better understanding of the necessity and
importance of the manufacturing testing process in product development. The intent and purpose for the dlesign and construction of the test machine, in this case, was thLat it would be used by students in other VLSI design and testing courses to test digital Application Specific Integrated Circuits (ASICs) that are fabricated through the MOS Implementation Service  (MOSIS) which is funded by the National Science Foundation [I]. Student designed ASICs fabricated through MOSIS are not tested (either at the wafer or package level) and are to be tested by the students as part of the educational process. As a result, a VLSI test machine is required to test the packaged devices for manufacturing defects after they are  shipped from the fabrication facility to the university. The
test machine described in this paper is capable of testing 40- pin, 600 mil Dual In-line Packages (DIPS) - the basic package type for the MOSIS TinyChipTM. However, the basic test machine design is scaleable to any size of packaged device assuming an appropriate socket is available. In the following sections we describe the test machine architecture and operation (Section 11), hardware design (Section 111), and software (Section IV). In the conclusion (Section V), we
describe the usage of the test machine to date and how this project enhanced students’ understanding of fundamentals of manufacturing testing.The complete test machine consists of both hardware and software components. The interface between the hardware and software is compatible with most DOS based Personal Computers (PCs) via the standard PC parallel (printer) port as illustrated in Figure 1. The software component, running on the PC, interprets user supplied
information including the input/output (I/O) pin definitions (or configuration) of the ASIC to be tested, as well as the set
of test patterns to be applied to the ASIC under test and the associated set of expected output responses. The software
then transfers this information to the hardware component via the parallel port. The hardware component, in tum, applies the input test pattems to the appropriate inputs of the ASIC under test and collects the resultant output responses. The software component subsequently retrieves the output responses from the hardware component for comparison with the expected output responses supplied by the user to determine the pass/faiI status of the VLSI device. A faulty status of the ASIC under test is reported to the user in terms of which output pin(s) failed during which test vector(s).



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