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Teaching Top-down Design Using VHDL and CPLD

Abstract
This paper presents a teaching experience in using
VHDL and CPLD in the senior digital design course. The
course focus on teaching the top-down design
methodology through hands-on experiments. The
industrial available tools — Maxplus2, made possible
through Altera’s University Program, provide our
students a smooth transition from academic concepts to
industrial practice. VHDL, the industrial standard
language (IEEE-1076), is used as the design entry. Thus,
the students are forced to learn the practical aspect of
writing a synthesizable VHDL code. The hands-on weekly
projects are exercised on the integrated CPLD design
tool which has VHDL compiler, logic synthesizer,
functional and timing simulator, floor plan editor and
programmer. With the help of programmable devices,
students can bypass the waiting period for IC fabrication
and obtain ASIC designs after the devices have been
programmed.
The VHDL design entry in Maxplus2 is ideal for
teaching top-down design methodology. Translating from
a given Algorithmic State Machine (ASM) chart to a
synthesizable and efficient VHDL code is presented.
Exploiting the VHDL constructs to make a design
reusable is demonstrated through examples. In this
course, students learn how to partition a complex design
into small components and focus on higher level of
abstraction and hierarchy in design description which
have become desirable to digital systems designers.
Introduction
In recent years, CPLDs (Complex Programmable
Logic Devices) have increased dramatically in capacity
and complexity. CPLDs with 100K gates are available in
today’s technology. To cope with the complex design,
higher level of abstraction and hierarchy in design
description have become desirable to digital systems
designers. Today, system-level logic design is most likely
a team work, forcing modular and hierarchical design
approach. Moreover, exploiting many technology
(implementation) options without translation of the
source design description is an increasingly important
requirement. The IEEE-standard (i.e. IEEE-1076) VHDL
language addresses these needs.
VHDL can be used to describe hardware from the
abstract to the concrete level. Many of the EDA
(Electronic Design Automation) vendors are
standardizing on VHDL as input and output from their
tools. These tools include simulation tools, synthesis
tools, layout tools, testing tools, etc. Due to the recent
advances in high-level synthesis tools, the text-based
design entry has gained increasing popularity in the
ASIC design. In our senior design course, we introduce
VHDL as the design entry in the CPLD design
environment. This course focuses on how to write VHDL
code that can be processed by synthesis tools [2].
The course begins with a brief summary of the
syntax of VHDL and is followed by several examples of
hardware modelling. The examples include simple
combinational logic, sequential models and finite state
machines. Applications of VHDL to top down design
methodology are presented. Specific design trade-offs in
CPLD for performance and efficiency are also discussed.
We employ the industry standard language,
VHDL, and a commercially available CAD tool
(Maxplus2[1] from Altera) in a set of hands-on weekly
laboratory experiments. These labs, in concert with a
semester design project, provide our students with a
smooth transition from the abstractions of academe to the
realities of engineering practice.



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