Superscalar power efficient Fast Fourier Transform FFT architecture

We develop Superscalar Architecture to compute fixed point FFT (Fast Fourier Transform). Some high-speed and time sensitive real time applications demand far better and efficient implementation of FFT and call for improved novel architectures. This account for bringing in place an embedded custom hardware for instance FPGA that helps us rally things in parallel yielding better performance. We take up established pipelined architectural models and coalesce into new efficient and power thrifty parallel-pipelined architecture that we call superscalar. Recognizing power efficiency, that is inherent architecture, is the key feature of this work. The work outlines ways to manipulate apparently intricate yet promising nature of FFT while obviating much of the potential complexity involved. This might be a long way to ultimate High performance custom hardware computing FFT.

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