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SEAMS: simulation environment for VHDL-AMS

VHDL-AMS is an analog and mixed-signal extension to the Very High Speed Integrated Circuit Hardware Description Language (VHDL). With the standardization of VHDL-AMS, capable and efficient simulators are in demand for exercising complex analog and mixed-signal models. The simulation of the language requires the ability to handle several levels of design hierarchy, the combination of multiple domains of modeling and the synchronization of continuous and discrete-event simulation. The expressive power of VHDL-AMS is also conducive for creating large simulation models. Large models have high resource demands especially on memory and execution time making parallel simulation no longer an option but a requirement. This paper introduces the issues involved in the design of a VHDL-AMS simulator and illustrates the simulation approach provided by SEAMS a parallel VHDL-AMS simulator. A performance study is presented to analyze the effectiveness of mixed-signal simulation using SEAMS



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