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An optimal partition between on-chip and on-board interconnects

Abstract
An optimal partition between on-chip and on-board
interconnects is proposed, which achieves the highest possible
global clock frequency as well as high wiring density. A
general model is developed for adequate number and size of
repeaters and the impact of this model on optimal partition of
interconnects is also studied. Using on-board wires the global
clock frequency of a projected system-on-a-chip in year 201 1
can be increased by about 45% and the required silicon area for
repeaters can also be reduced by 60%, using adequate repeater
insertion.
Introduction:
As technology advances delay of transistors and local
interconnects scales down and in this way the local clock
frequency is projected to increase rapidly. Scaling the
transistors makes local interconnects shorter and results in
smaller delay. However, since chip area is projected to
increase, length of global interconnects increases and therefore
their delay increases. The key solutions for reducing delay of
global interconnects are increasing the wire cross-sectional area
and inserting repeaters. However, using fat wires decreases the
wiring density.
On the other hand off-chip interconnects usually have
very large cross-sectional area and therefore, they have
negligible loss, which results in time-of-flight (ToF) delay.
New packaging technologies such as high-density compliant
wafer level packages [ I ] provide very dense pad arrays with
negligible parasitics. In this way some of the long global
interconnects may be routed through the printed wiring board
(PWB). However, since PWB wiring density is sm’all, very few
interconnects may be routed through the board and the optimal
number of these long external interconnects or “exterconnects”
should be rigorously calculated.
An optimal on-chip wire width, which results in small
delay as well as high wiring density, is found for different
generations when optimal repeaters are used. Then an optimal
partition between on-chip and off-chip interconnects is
introduced, which results in highest performance. Since optimal
repeater insertion requires too many large repeaters, a generic
model for the adequate number and size of repeaters is found
and its impact on optimal width and maximum length of onchip
interconnects is determined. Finally for a projected
system-on-a-chip performance and cost of different approaches
are compared.
Optimal Partition between On-Chip and On-PWB Wires
Assuming an RC model is valid, the delay of an
interconnect using optimal repeater insertion is [2]
5 = 2.5 e,/-, (1)
w
where ! and w are the wire length and width, p is the metal
resistivity, Ro and CO are the output resistance and input
capacitance of a minimum size repeater. is the dielectric
constant and k is a constant, which is determined by geometry.
For the geometry shown in Figure 1 when the aspect ratio is
unity, k=5.53 [3].
Equation (1) is valid for small and when it gets large,
inductance cannot be neglected. Optimal number of repeaters
and their size are also given considering inductance impact [4].
Using those optimal values and Hspice simulations, delay of
wire versus wire width is shown in Figure 2. All parameters are
International Technology Roadmap for Semiconductors (ITRS)
projections for year 201 1 [5]. The skin effect is also considered
when wire thickness is comparable with skin depth.
Figure 2 shows as long as RC model is valid increasing
the wire width decreases the delay by the same ratio. However,
when the wire width gets large enough so that the RC model
deviates from the RLC model, increasing the wire width does
not decrease the delay significantly and therefore, it is not
reasonable to have such a large wire width. Wire width, which
results in a roughly 10% difference between RC and RLC
models is an optimal value for on-chip wire width because it
has a small delay as well as high wiring density (02 is
minimized). Figure 3 shows that the optimal wire width does
not depend on wire length. It happens when RC delay is equal
to 1.33 time of flight delay. By Substituting the above
condition in (1) the optimal wire width can be found:
w“,,~= 1. 8 8 c 0 , / m 9 (2)
where co is the speed of light in vacuum. mopd, epends solely on
resistivity of metal, intrinsic delay of a repeater, and the
geometry of wire. Figure 4 shows the optimal wire widths for
different generations and aspect ratios based on ITRS
projections. It is important that keeping the wire width equal to
the optimal values makes the wire dimensions smaller than
twice skin depth, which means the skin effect is negligible and
interconnect metal is used efficiently. Remaining in RC region
also makes far inductive coupling less serious and makes
design process easier. On-chip interconnects usually have no
ideal return path and therefore, inductance may cause voltage
overshoots up to 50% higher than Vdd, which may damage the
gate oxide [6]. Hence, avoiding the RLC region also increases
the reliability.
The global clock frequency of a System-on-a-Chip is
usually determined by the largest interconnect delay and
therefore, ideally it will be equal to the reciprocal of the timeof-
flight delay of the longest interconnect. However, ToF delay
for on-chip interconnects requires prohibitively large wide
wires and thick dielectrics and also an ideal return path, which
is a ground plane.
Printed Wiring Board (PWB) wires usually have a large
cross-sectional area and therefore, if they are terminated
properly, have time of flight delay. If some of the long
interconnects are routed through PWB “exterconnects”, the
maximum on-chip interconnect then reduces and as (1) shows,
the maximum delay reduces. If the maximum on-chip
interconnect length decreases so that the maximum on-chip
delay becomes equal to the ToF delay of the longest
interconnect (a comer-to-comer interconnect) then the
maximum possible global clock frequency is achieved. Hence,
the maximum on-chip interconnect length can be found by
E, = 0.75(20,,,). (3)
0-7803-6678-6/0U$l0.000 2001 IEEE 131
where DCh, is the chip edge size. All interconnects for
e,<! <2Dc,,,p should be on-PWB to have the highest
global clock frequency. This method reveals the optimal
partition between on-chip and on-PWB interconnects for the
global net distribution of a SoC and maximizes the global clock
frequency without loosing on-chip wiring density.
Because of on-board ground planes exterconnects
crosstalk is minimum, local and well known. They also have no
overshoot problem and unlike on-chip interconnects have
negligible delay variation.



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