The Nibbler teaching microprocessor project

Nibbler is a simple microprocessor designed as the basis of a third year undergraduate VLSI fabrication project. Nibbler is not a high performance processor-wherever possible the hardware has been simplified to reduce the opportunity for design errors. The resulting design requires about 2-3,000 transistors for a CMOS full custom implementation. A cross-assembler and behavioural simulator are available. Approximately 30 undergraduates take the VLSI design course annually. In 1990 about two-thirds of the projects have been based on the Nibbler architecture implemented using three different toolsets and various design strategies. Teams of up to six students have collaborated in the larger projects in an attempt to simulate industrial working practices


Programmer’s view
A basic processor datapath typically inciudes an ALU. a shifter, registers and multiplexing to external
data buses. Nibbler adds minimal instruction sequencing and decoding logic to this basic datapath to
form a complete processor.
Nibbler is rather primitive compared to commercially available microprocessors. Internally it is
an eight bit device, but main memory is organised in four bit nibbles so as to reduce the number of
package pins required for the data bus. The instruction sec is strictly register to register, except for
the LD and ST instructions which move data between r-gisters md memory.
Sixteen general purpose registers are grouped in pairs which may be used as sixteen bit pointers
into memory. A status register is updated after arithmetic and logic instructions and can be tested
using a conditional jump.
Although sixteen eight-bit general purpose registers are visible to the programmer, the lower two
(RO and RI) form the program counter, so only fourteen registers are free for use by the program.
In addition, the LD, ST and JMP instructions require a pair of registers for use as a memory address
pointer, and memory loads usually require a scratch register in which to assemble a byte from two
memory nibbles. By convention register pairs (R3,R2) and (R5.R.4) are used for pointers and register
R6 and R7 are used for scratch storage. This leaves eight registers for program data.
The fourteen instructions are summarised in the table below.
The two address instructions are of the form Op src dst and implement operations of the form dst
:= src Op dst where src and dst are registers in the range 0-15. Single address instructions are of the
form Op dst and implement dst := Op dst.
The LD and ST instructions take a register number and a pointer register number, which must be
even. The contents of the pointer register and the register above are concatenated to form a sixteen
bit memory address. LD loads the addressed memory nibble into the low nibble of the destination
register. The high nibble is cleared. ST copies the low nibble of the register to the addressed memory
The JMP instruction takes a condition and a pointer register. Ten different conditions may be
tested for. Lf the condition is true the pointer is transferred to the program counter causing a jump
to the pointer location.
The SE instruction takes a register and a four bit signed number which encodes a shift value
of between -8 and f7. Positive values shift up and negative values shift down with zeroes being

propogated into the register. A shift value of -8 effectively fds the register with zeroes, and a shift
value of 0 acts as a no-operation.
The instructions described above include no explicit provision for loading constants. However, the
presence of the program counter w i t h the main register stack enables constants to be stored in the
instruction stream and loaded by the standard LD instruction using the program counter as a pointer.
This mechanism is inspired by the immediate addressing mode of the PDP-11 (Be178, pages 251-2551,
As a special case, when RO (the program counter) is used in a pointer operation it is incremented
after the main memory location has been accessed. This is necessary to ensure that the constant is
skipped in the instruction stream and not loaded for execution.

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