Nano tech

2.1 PRESENT STATE OF NANO-ELECTRONICS. Moore's law states that the number transistor on an integrated chip for a component doubles every two years. How ever this law does not holds perfectly true for RAM (Random Access memory). This does not mean that the number of transistor on a chip increases but about the density of transistors at which the cost per transistor is the lowest.Currently processors are fabricated at 90nm and 65nm that are being introduced by Intel. The 90 nanometer (90 nm) process refers to the level of semiconductor process or fabrication technology that wasachieved in the 2002-2003 period, by most leading semiconductor companies, like Intel, Texas Instruments, IBM etc. However it is not true for RAM and hard disk. New materials seeing possible use in nano-electronics and will probably keep this law on track. The future is seen as molecular electronics but there is lots of work still to be done to make that possible.
2.2.1 CMOS Nanotechnology
For the past several decades, miniaturization in silicon integrated circuits has pro- gressed steadily with an exponential scale described by Moore's Law. This incredible progress has generally meant that critical dimensions are reduced by a factor of two every three years, while chip density increases by a factor of four over this period. However, modern chip manufacturers have been accelerating this pace recently, and currently chips are being made with gate lengths in the 45 to 65 nm range. More scaling is expected, however, and 15-nm gate lengths are scheduled for production before the end of this decade.
In MOSFET there is electric field between the gate and the semiconductor is such that an inverted carrier population is created and forms a conducting channel. This channel extends between the source and drain regions, and the transport through this channel is modulated by the gate potential. As the channel length has gotten smaller, there has been considerable effort to incorporate a variety of new effects into the simple (as well as the more complex) models. These include short-channel effects, narrow width effects, degradation of the mobility due to surface scattering, hot carrier effects, and velocity overshoot. Ballistic transport in the MOSFET (discussed in later part) Thermodynamics is just as significant in limiting scaling as the preceding effects. The first way it limits scaling is in its control of the subthreshold behavior of MOSFETs. The subthreshold current of a MOSFET originates in the high-energy tail of the statistical distribution of carriers in its source region. The carriers in the source are governed by Fermi-Dirac statistics, and so the tail of the distribution is essentially Boltzmann.
There two major scattering regions - the barrier between the channel and the source and within the channel.
There also exists a phenomenon Granularity is the failure of thermodynamic averaging in small devices. Quantum behavior in the device, there are two effects and Effective Carrier Wave Packet . These effects also include tunneling through the gate insulator, tunneling through the band gap, quantum confinement issues, interface scattering, discrete atomistic effects in the doping and at interfaces, and thermal problems associated with very high power densities.
Ballistic Properties:-
It is the phenomenon where the the contribution in electrical resistivity due to scattering by the atoms, molecules or impurities in the medium itself, is negligible or absent meaning the electron can move without hindrances. There is no loss of kinetic energy due to collision of hitting of electrons with atom of metal thereby electrons move in a mean free path where it can move freely.
Quantum mechanical scaling limitations include both confinement effects and tun- neling effects. Confinement effects occur when electron or hole wave functions are squeezed into narrow spaces between barriers. In FETs this primarily happens in the channel, where the charges are squeezed between the gate insulator on one side and the built-in field of the body on the other side. Quantum confinement in this approximately triangular well raises the ground state energy of the electrons or holes, which increases the threshold voltage, and shifts the mean position of the carriers a little farther from the Si-SiO2 interface. Quantum mechanical tunneling is generally more detrimental to scaling than the Confinement effects. When electrons or holes tunnel through the barriers of the FET, it causes leakage current. As scaling continues, this ultimately causes unacceptable increases in power dissipation. The leakage may also cause some types of dynamic logic circuits to lose their logic state, but the former problem usually seems to arise first.
There are primarily two forms of tunneling leakage: tunneling current through the gate insulator, and tunneling current through the drain-to-body junction. The atomistic effects that cause limitations to scaling are those in which the discreteness of matter gives rise to large statistical variations in small devices. These statistical variations occur because the atoms or molecules tend to display Poisson statistics in their number or position, and the Poisson distribution for small numbers can become very wide.
2.2.2 Memory
As the semiconductor device feature size enters the sub-50-nm range, two new effects come into play. One is the quantum effect, which is rooted in the wave nature of the charge carriers, and gives rise to non classical transport effects such as resonant tunneling and quantum interference. The other is related to the quantized nature of the electronic charge, often manifested in the so-called single-electron effect: Charging each electron to a small confined region requires a certain amount of energy in order to overcome the Coulomb repulsion; if this charging energy is greater than the thermal energy, kb*T (kb Boltzman constant, T temperature), a single electron added to the region could have a significant effect on other electrons entering the confined region.
To increase the storage density of semiconductor memories, the size of each memory cell must be reduced. A smaller memory cell also leads to higher speed and lower power consumption. This is the incentive for studying the nanoscale semiconductor memory. One of the general schemes for semiconductor data storage is by storing charges on a capacitor. The charged state and the uncharged state can be used to represent binary information 1 and 0, respectively. Usually charges are transferred to the capacitor through a resistive. The motivation for this work is to investigate the ultimate limit of a floating gate MOS memory. In a conventional floating gate memory, there are typically on the order of 10 to power 4 electrons stored on the floating gate to represent one bit of information. The ultimate limit in scaling down the floating gate memory is to use only one electron for the same purpose, hence the name "single-electron MOS memory" (SEMM). The advantage of such a memory is that not only can it be very small, but also it can provide some unique characteristics that are not available in the conventional device, such characteristics as quantized threshold voltage shift and quantized charging voltage.
To make single-electron memory practical, both thermal fluctuation and quantum fluctuations of the stored charge have to be minimized. In order to reduce the variation in the device structure, we would like to build a single-electron memory device in crystalline silicon that has well-controlled dimensions. We defined the transistor channel and the floating gate by using lithography. Finally, the single-electron memory potentially has a number of advantages over conventional memories: (1) the quantized characteristics of the device make it immune to the noise from the environment-unless the noise level reaches a certain threshold, it will not affect the memory state. The immunity to noise is especially important for the future terabits integration, simply because of the sheer large number of devices present on a single small chip area. (2) the inherent quantized nature of the SEMM makes it possible to easily implement multilevel logic storage in a single memory cell; (3) the device can operate at a higher speed due to the use of only one or few electrons during writing and erasing; (4) for the same reason, the device can also have ultralow power consumption.

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Sat, 11/06/2011 - 14:53

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