Modelling VHDL in multiclock ESTEREL

The introduction of HDLs (hardware description languages) have made a significant contribution to VLSI circuit design. While these languages are well suited to describe circuits in great detail, they are found wanting when attempting formal verification of circuits. One of the drawbacks lies in the lack of formal models of semantics. VHDL, with a wide variety of tools available to carry out circuit simulations, is the de facto standard used in VLSI design. On the other hand, the family of synchronous languages has been well studied for the design and synthesis of provably correct reactive systems. Thus, it behooves one to explore the possibility of interfacing languages such as VHDL with synchronous programming languages to handle higher levels of abstraction in circuit design with assured correctness. In this paper, we show how the paradigm of multiclock ESTEREL provides a framework for the design of multi-clocked systems and asynchronous systems. Multiclock ESTEREL can be used for modeling in conjunction with VHDL to enable formal verification of circuit behavior. We also show that multiclock ESTEREL captures the VHDL timing model succinctly. Multiclock ESTEREL can be used either in conjunction with VHDL or as a replacement depending on the requirements at hand. When used in conjunction, Multiclock ESTEREL can be used to describe circuits at higher levels of abstraction while VHDL can be used to describe the signal propagation characteristics

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