The MIT Vision Chip Project: analog VLSI systems for fast image acquisition and early vision processing

The goal of this project is to design and build prototype
analog early vision systems that are remarkably lowpower,
small, and fast. This paper briefly outlines the
overall project and describes two tested chips in some
1 Introduction
In real-time machine vision the sheer volume of image
data to be acquired, managed and processed leads
to communications bottlenecks between imagers, memory
and processors, and to very high computational
demands. A group at MIT is designing experimental
analog VLSI systems to overcome these problems. The
work is presently concentrated entirely on early vision
tasks, i.e., tasks that occur early in the signal flow path
of a machine vision system. Designs of chips for certain
tasks in velocity estimation, image moment calculations,
depth from stereo, and edge detection are currently
underway or have been completed. A detailed
description of the project can be found in [l].
This project began in September 1988, and the faculty
involved are Profs. Berthold Horn, Hae-Seung Lee,
Tomaso Poggio, Charles Sodini, Jacob White and John
Wyatt, principal investigator. It was inspired by Prof.
Carver Mead’s pioneering efforts at Caltech, although
it differs from Mead’s in both methods and goals.
The goal of this project is to design and build prototype
early vision systems that are remarkably lowpower,
small, and fast. The typical system will perform
one or more computation-intensive image-processing
tasks at hundreds to thousands of frames per second
*Currently at the Imaging Devices Dept., Science Center,
t Currently at the Division of Applied Sciences, Harvard Uni-
Rockwell International, Thousand Oaks, CA, 91358.
versity, Cambridge, MA, 02139.
using only tens to hundreds of milliwatts. The entire
system with lens, imager, power supply and support
circuitry can fit inside a cigar box.
The project is exploring the possibilities of various
types of analog processing for early vision. There is no
single design strategy, but each of the designs has many
of the following features:
sensors and processing circuitry integrated on a
single chip,
parallel computation,
analog circuits for high speed, small area and low
selection of tasks and algorithms requiring low to
moderate precision (roughly equivalent to 6-8 bit
fixed point precision in a digital machine),
special emphasis on computations that map naturally
to physical processes in silicon, e.g., to relaxation
processes or to resistive grids,
emphasis on charge-domain processing, e.g., CCD
and switched-capacitor implementations, for maximal
layout density and compatibility with CCD
sufficiently fast processing that no long-term strorage
circuitry is required, and
careful matching of algorithms, architecture, circuitry
and (often custom) fabrication for maximum
The advantages of this analog design approach to
early vision hardware are high speed (both in the sense
of high throughput and low latency), low power, and
small size and weight. High throughput can be important
in high speed inspection processes, e.g., for printed

materials or PC boards. Low latency is very important
for closcd loop systems because delays are destabilizing.
Relevant examples might include vehicle navigation
and robot arm guidance. Low power together with
small size and weight are important for airborne and
space applications. And finally, small systems tend to
bc affordable.
These advantages are achieved at a cost. One is the
high degree of care and expertise required for high performance
analog design. Another is that performance
and even functionality of analog integrated circuits is
critically dependent on exact fabrication process paramebers.
For these two reasons the first design of
an analog chip, even by an experienced designer, often
doesn’t work at all and repeated efforts are required.
Another problem is the large amount of labor and frequent
dclays involved in custom fabrication on campus.
Finally, analog systems have little flexibility compared
with their digital counterparts. Thus analog design,
often coupled with custom fabrication, is only appropriate
when extremely high performance is required.
Chips are fabricated through MOSIS whenever possible.
Chips requiring special processing are fabricated
on campus in MIT’s Microsystems Technology Laboratories.
A special CMOS/CCD fabrication process has
been developed there by Craig Keast and Prof. Charles
Sodini for vision applications.
Sections 2 and 3 describe chips that have been designed
and tested by David Standley and Woodward
Yang, respectively, as doctoral students in this project

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