Measuring HDL-based design productivity: an experimental comparison

Abstract: Two process models for top-down
HDL-based design are developed in order to
measure HDL-based design productivity. A
sorting algorithm is used as a benchmark to
experience various design activities in HDL entry
and mixed entry design process models. We
measure the effort (time) required for each
design activity and analyze the "effortdistribution"
over various design activities. We
also discuss the resources that are essential to
perform each design activity. These experiments
demonstrate the applicability of "effortdistribution
analysis" to enhance design
productivity in real l$e design projects.
Keywords: Activity-centered model, design
productivity, effort-distribution, HDL entry, IS0
9000, mixed entry, resources, top-down design
1. Introduction
The advent of hardware description languages
(HDLs) has been a blessing to the design
community, where designers aim to represent
complex digital systems at a higher level of
abstraction. Thanks to the gamut of electronic
design automation (EDA) tools based on
industrial standards such as Verilog HDL and
VHDL, HDL-based design methodologies have
attracted substantial amount of attention [6].
For a given set of requirements, it is desirable
to know how much it will cost to develop the
design. Given a design environment with
adequate software (tools, compilers, etc.) and
hardware (workstations, PCs, etc.), the bulk of
the cost lies in human resources needed [7]. Most
cost models represent these in terms of person-
.The research reported in this paper was supported in part
by Ricoh Company Ltd.
months (PM) or man-hours (MH). This paper
uses an activity-centered model [2] to analyze the
effort-distribution over various activities in the
top-down HDL-based design process. Figure 1
shows a unit activity model.

Each design activity provides an output in
response to an input from the previous activity
along with design effort and resources. The
resource input comprises of the hardware and
software resources in addition to the designer's
experience. The term "experience" implies
familiarity with the design language, tools and
working environment. In order to include the
"experience" parameter, as a component of the
resource input to the model shown in Figure 1,
the time for learning HDL support tools is
recorded as an indirect design effort.
Design experiments were carried out by two
designers using a sorting algorithm as a design
benchmark, by performing the design froin a
problem statement to a working netlist in Verilog
HDL-based design environments.

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