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The impact of floorplanning on the yield of fault-tolerant ICs

Abstract
Until now, VLSI designers rarely considered yield issues when selecting a floorplan for
a newly designed chip. This paper demonstrates that for large area VLSI chips, especially
those that incorporate some fault tolerance, changes in the floorplan can affect
the projected yield. We study sevcral general floorplan structures, make some specific
recommendations, and apply them to actual VLSI chips.
1. Introduction
When designing a new chip, yield issues rarely affect the choice of the floorplan. This
is justified when the chip is relatively small and the defect distribution can be accurately
described by either the Poisson or the compound Poisson yield models ([l])I.n particular,
in the most commonly used compound Poisson model, i.e., the negative binomial (NB)
distribution with large area clusterl~ng [2], the “size” of the defect clusters is assumed to
be much larger than the size of the chip and selecting a different floorplan will not affect
the projected yield of the designed chip.
Recent studies of defect maps of very large area VLSI ICs [3] have shown that the
large area clustering NB distribution does not provide a sufficiently accurate yield model
for such ICs. The newly proposed medium size clustering model [4] provides a much
better match to empirical data [3]. Our objective is to study the possible impact that
the floorplan of a large area chip (vviith or without redundancy) would have on the yield
of the chip, under the new medium area clustering NB yield model.
In [5] we performed a prelimimry study using two actual test cases, namely, DEC’s
Alpha chip [6] and Hitachi’s SLSI (System integrated LSI) chip [i’]. Our conclusion
was that the floorplan of a chip can affect the projected yield of the chip in a nonnegligible
way. In this paper we perform a more detailed study of the relationship between
floorplanning and yield. We analyze several general problems and propose theoretical
solutions for them. We then make some practical recommendations and illustrate them
through two actual test cases.



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