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High-speed VLSI architecture for parallel Reed-Solomon decoder

This paper presents high-speed parallel RS(255,239) decoder architecture using a modified Euclidean algorithm for the high-speed fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber optic rates and outputs to be delivered at correspondingly high rates with minimum delay. Parallel processing architecture results in a speed-ups of as much as or more than 10 Gbits/s, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean algorithm block. The parallel RS decoders have been designed and implemented with the 0.1 3-μm CMOS standard cell technology in a supply voltage of 1.1V. It is suggested that a parallel RS decoder, which can keep up with optical transmission rates, i.e., 10 Gbits/s and beyond, could be implemented. The proposed channel=4 parallel RS decoder operates at a clock frequency of 770 MHz and has a throughput of 26.6 Gbits/s.



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