Projects

High-level system modeling and architecture exploration with SystemC on a network SoC: S3C2510 case study

This paper presents a high-level design methodology applied on a network SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the project with working Verilog RTL models in hands, which we later compared our SystemC models to. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.

 

Introduction
As SoC has started to dominate the ASIC world, the
competitiveness of performance and price have increased
and triggered the market to move accordingly. Customers
request higher performance chip with lower price.
In order to meet such demands, many companies have
tried to adopt high-level design methodology to measure
and analyze the chip before fabrication or even before
RTL development. Not only to adopt or create a new highlevel
design methodology, many companies also want to
have an assurance on the performance after the chip is
manufactured. To satisfy all the above and shorten the
Turn-Around-Time (TAT), we integrated SystemC[2] into
our design flow and applied Transaction Level Modeling
(TLM) method.
One of our Network SoC’s, S3C2510[1], was already in
2Samsung Electronics Co., Ltd.
Gyeonggi-Do, Korea
{minsoo.kang , artistic.lee, corean, kookpyo.lee,
kh.shim}@samsung.com
production. However, the performance of the network SoC
did not meet the initial expectation. When the frame was
transmitting at 98 Mbps, it was receiving it only at 52
Mbps. It was roughly losing half of its packets. Even
though, the current performance was acceptable in the
market for the time being, we had to diagnose the
performance bottleneck and provide a solution for the
improvement.
As many hardware engineers have agonized for many
years, it was impossible to explore the architecture once
the chip was fabricated. Even in Register Transfer Level
(RTL), it was almost impossible to port Real Time
Operating System (RTOS) and do many different cases of
architecture exploration in limited design time.
Darringer et al.[7] at IBM explained the method for
architecture exploration and model validation. Even
though they showed architecture exploration in many
different areas, they were not able to achieve the accuracy
or the simulation speed as we have.
In this paper, we will present a method of architecture
exploration in transaction level while keeping the RTLlike
accuracy and achieve over one hundred times faster
simulation speed than that of RTL’s. Moreover, it will
show method of RTOS porting and some unexpected
problems on a virtual system. Finally, it will explore CPU
profiling and



Tags :
5
Your rating: None Average: 5 (1 vote)