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Hierarchical mixed-level simulation of VHDL descriptions

We present a hierarchical multilevel VHDL simulator for large systems described at the transistor, gate and higher levels. We exploit the hierarchy and regularity in VHDL descriptions to reduce the memory requirements drastically. The simulation algorithm handles MOS digital designs with bidirectional signal flow. We have augmented VHDL descriptions with signal strengths and timing; and also proposed a method to extend VHDL to accept transistor-level descriptions. Simulation results are provided for sample VHDL circuits



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