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HDL and integrating system-level simulation technologies

System-level design is a critical component of any
electronics product development project. However, HDLbased
ASIC design has remained a distinctive and separate
function within projects. With the advent of deep
submicron technology, large systems and subsystems can
now be placed on a single chip. This requires a closer
interaction between system-level design and ASIC
development.
This paper describes an effective methodology and
technology support for integrating system-level simulation
techniques with HDL-based simulation to provide a smooth
transition between each level. We start by examing an
integrated verification methodology and the use models for
utilizing mixed dataflow and HDL models. We then discuss
combining a model of interaction derived from the work
done on the Ptolemy project with a standards-based
implementation approach using the Open Model Forum
(OMF) standard. Finally, an example is used to highlight
the effectiveness of this approach.
1. Introduction
In today's environments for electronic systems design,
there is often a clear separation between individuals
working on the functionality and algorithms for a given
system and the teams implementing custom hardware
within those electronic systems. Distinct methodologies
have evolved for modeling and verifymg descriptions of
both the systems view and the hardware view. Most
system-level description are variations of process networks
which communicate through tokens including dataflow
networks, concurrent FSMs, and queuing descriptions. For
custom hardware, standard HDLs (VHDL and Verilog) are
the most common representations.
This separation of modeling approaches for systemlevel
design and custom hardware block implementation
was sufficient for most systems. However, there has
always been a motivation to tie these two levels closer
together, especially in the case where a given function was
being implemented directly as a custom hardware block.
As more and more functionality is mapped onto single
chips which include not only custom hardware blocks but
also reusable, on-chip components (cores, megacells), an
integrated methodology for both system-level design and
chip implementation becomes critical.
In order to provide supporting technology for this new
integrated verification methodology, he Alta Group of
Cadence has been analyzing approaches for heterogeneous
simulation of multiple computation domains. In addition,
we have been looking at the encapsulation of models
described using a particular compuational domain within
other domains. In general, we have chosen to adopt the
approaches taken within the Ptolemy project with some
exceptions. In addition, we have adopted the OMGI
interface (from the OMF standardization effort) as a
general mechanism for implementing Ptolemy semantics.



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