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Estimating crosstalk from VLSI layouts

Signal integrity problems have been reported as the primary sources of chip failure in many deep submicron VLSI projects. Crosstalk due to coupling capacitance between adjacent wires that run very closely to one another can result in both logic and delay faults. A CAD tool that can analyze a VLSI layout and point out sources of potential crosstalk problems is therefore highly valuable. In this paper we report a tool called MACE which can do so with a good degree of accuracy without actually performing detailed circuit simulation. Comparisons with accuracy SPICE simulation using industry-standard circuits as benchmarks reveals that the error in MACE analysis is less than 15%. The computational time requirement of the MACE tool, on the other hand, is in minutes as compared to circuit simulation which requires hours of computation for industry-standard circuits



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