Dual Clock Synchronous RAM

This example describes a 64-bit x 8-bit dual clock synchronous RAM design with different read and write addresses in Verilog HDL. Synthesis tools are able to detect dual clock synchronous RAM designs in the HDL code and automatically infer either the altsyncram or altdpram megafunctions, depending on the architecture of the target device.

Figure 1. Dual Clock Synchronous RAM Top-Level Diagram

Figure 1. Dual Clock Synchronous RAM Top-Level Diagram

Table 1 lists the ports in the dual clock synchronous RAM design.

Table 1. Dual Clock Synchronous RAM Port Listing
Port Name Type Description
data[7:0] Input 8-bit data input
read_addr[5:0] Input 6-bit read address input
write_addr[5:0] Input 6-bit write address input
we Input Write enable input
read_clock Input Read clock input
write_clock Input Write clock input
q[7:0] Output 8-bit data output

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