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Design of reconfigurable logic controllers from hierarchical UML state machines

The paper presents a formal design methodology for reconfigurable, modular digital controller logic synthesis. The project of embedded controller starts from behavioral, graphical hierarchical and concurrent state machine description in Unified Modeling Language (UML). After the hierarchical encoding of nested and concurrent superstates, the UML state machine diagram can be directly and automatically mapped into the structured array of cells in Field Programmable Gate Array (FPGA). The design process goes through rule-based symbolic assertions on the behavioral level to propositional logic expressions in Register Transfer Level, which are automatically rewritten in Hardware Description Languages (VHDL or Verilog). The transformation from specification to implementation is partially supported by a computer theorem prover changing the symbolic form of complex UML state machine specification given in the Gentzen sequent logic into simple textual rule-based statements. They are directly accepted by commercial HDL tools for simulation and effective logic synthesis.



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