Design of Programmable Logic-BIST Structures Using Verilog for Digital VLSI Circuits

Abstract— Built-in self-test for logic circuits or logic BIST , is
an effective solution for the test cost, test quality, and test
reuse problems. Logic BIST implements most ATE functions
on chip so that the test cost can be reduced through less test
time, less tester memory requirement, or a cheaper tester.
Logic BIST applies a large number of test patterns so that
more defects, either modeled or un-modeled, can be detected.
In addition, logic BIST makes it easy to conduct the at-speed
test for detecting timing-related defects. Furthermore, a
BISTed- core makes SoC testing easier. Most of logic BIST
schemes are based on the STUMPS structure, which applies
random patterns generated by a PRPG to a full-scan circuit
in parallel and compresses the responses into a signature
with a MISR. This paper summarizes a flexible logic BIST
scheme that implements the above structures.
Design for Testability (DFT) is the name for design
techniques that add certain testability features to a digital
VLSI circuit. The major three approaches to DFT are
given as:

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