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Design and verification techniques used in a graduate level VHDL course

The use of the VHSIC Hardware Description Language (VHDL) has become very important to the simulation and implementation of digital systems in both industry and educational settings. Although VHDL is a powerful language with many capabilities, it has downfalls when considering the difficulty in learning the language as well as its limited capabilities for transitioning a design from initial concept to design entry and verification stages. This paper discusses techniques used to teach the VHDL design methodology to graduate students, as well as methods used to go through a complete design cycle from initial concept to final implementation. VHDL design techniques were developed using various projects and homework assignments, and different approaches to implementing the same function allowed direct comparisons of the speed and size of the designs. Different processes for taking a design from initial concept through chip implementation were discussed, and one example of the process is discussed here. A Finite Impulse Response (FIR) filter was conceptually designed using the MATLAB programming environment to determine adequate performance specifications such as filter size and quantization levels. The design was then written using a behavioral VHDL coding style, as well as a VHDL test bench to determine if the VHDL behavioral model provided the same results as the MATLAB model. After design synthesis of the behavioral description using Synopys tools, the same test bench was used again to verify the performance of the structural VHDL netlist with annotated place and route delay information provided from the Alters MaxPluslI tools. Final verification took place with at the board level using an Altera CPLD programmed with the FIR filter design



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