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A cohesive FPGA-based system-on-chip design curriculum

Abstract
A graduate-level computer engineering course
sequence at the OGI School of Science and
Engineering teaches state-of-the-art digital system
design practices and system-on-chip design concepts.
Commercial electronic design automation (EDA)
software in conjunction with high-density
programmable logic devices allows students to design
projects of significant complexity. The course
sequence, targeted for both full-time students, and part
time students from local high-tech companies, consists
of three consecutive courses taught fall, winter, and
spring quarters. The first course covers logic design
using Verilog, the second introduces logic synthesis
and system-on-chip design concepts, and the third
addresses timing and test of digital systems.
1. Introduction
Advances in semiconductor technology have made
it possible to implement a complex system on a single
programmable chip. High-density FPGAs are an ideal
vehicle to teach system-on-chip (SoC) design because
the FPGA design cycle is short enough that students
can complete complex designs within the time-frame
of an academic quarter. Though FPGA implementation
is used throughout the course sequence, the SoC
design principles are taught in a way that is applicable
to ASIC implementation as well.
This three-course sequence is a core component of
OGI’s computer engineering curriculum, which also
includes courses in computer architecture, VLSI
design, circuit design, and digital signal processing.
The first course, EE570 Advanced Logic Design,
teaches logic design using the Verilog hardware
description language (HDL). The second course,
EE571 System-on-Chip Design with Programmable
Logic teaches logic synthesis and system-on-chip
design concepts. In this project-oriented course,
students design a series of SoC projects using an 8-bit
processor and a simple graphics subsystem, and
implement them in FPGAs. The final course, EE572
Advanced Digital Design: Timing and Test, completes
the sequence, focusing on timing issues, such as
timing-driven logic synthesis, static timing analysis
(STA), metastability, synchronization, and multi-clock
design techniques. Design-for-test topics such scan
testing and automated test pattern generation are also
introduced.
Verilog HDL is used rather than VHDL because it
is easier to learn and more widely used in local
industry. Mentor Graphics and Xilinx EDA software is
used throughout the course sequence. The ModelSim
logic simulator is used for design verification in all
three courses. Precision RTL Synthesis is used for
logic synthesis in both EE571 and EE572. Xilinx ISE
provides FPGA placement and routing in EE571 and
STA in EE572.
Students enrolled in the courses have access to
OGI’s Computer Engineering laboratory. The CE lab
is equipped with Xilinx FPGA development boards
from Digilent, Inc., signal generators, oscilloscopes,
and computer workstations with Mentor Graphics and
Xilinx EDA software installed.
Located in the heart of Oregon’s “Silicon Forest”,
the OGI School of Science and Engineering’s
computer engineering education program offers a
Master of Science degree in electrical engineering.
Most students work full-time in the technology
industry and attend school part-time. These students
are well prepared and have high learning expectations.



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