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On-chip Fault-tolerance Utilizing BIST Resources

Abstract- Recent and projected advances in VLSI fabrication
technology will allow for integration of billions of transistors
and advanced architectures on a single chip. According to the
International Technology Roadmap for Semiconductors
(ITRS), widespread reliability challenges are expected for these
VLSI fabrication technologies (65nm and below). Effective and
efficient on-chip fault-tolerance solutions are needed. A new
approach of achieving on-chip fault-tolerance using built-inself-
test (BIST) resources is proposed in this paper. The
proposed approach reduces production cost, implementation
overhead and time-to-market; increases reusability, postfabrication
reconfigurability and productivity; and is scalable
across multiple VLSI processes and feature sizes. This will
result in obvious advantages of yield enhancement and
prolonged lifetime of VLSI chips as well.
I. INTRODUCTION
With the introduction of multiple changes and shrinking
feature sizes in VLSI technologies, it has become possible to
fabricate billion-transistor chips. Emerging paradigms
utilizing these vast on-chip resources are system-on-chip and
multi-core architectures [1][2]. One of the major problems
being faced by architects of these systems, is to achieve
effective on-chip fault-tolerance without sacrificing too
much area, energy and performance.
To further elaborate on the problem, according to ITRS,
widespread reliability challenges are expected in near term
VLSI fabrication technologies (65nm and below) because of
the evolutionary changes in scaling current materials and
devices [3][4] and revolutionary changes associated with
new materials and devices. The introduction of multiple
materials, processes and structural changes in a short period
will increase the difficulty of understanding and controlling
failure modes. Therefore, fault-tolerance should be
considered a necessity, rather than as a feature.
Traditional redundant logic (like Triple Modular
Redundancy [5]), arithmetic coding and algorithm-based
fault tolerance (ABFT) approaches are limited in the type
and number of faults [6][7] they address, in addition to
introducing hardwired performance and very high
implementation overhead in designs (section IV). Traditional
approaches will require another fabrication run for more and
different types of faults, adding to the production time and
hence time to market, not to mention total cost of the
product. Thus, there is clearly a need for new fault tolerance
techniques.
Our philosophy is to take unknown faults, less fault
diagnosis and characterization time before production and
unknown failure rates as a specification for providing a faulttolerance
solution for future VLSI architectures. The above
requirements translate into a programmable flexible faulttolerance
solution. A post-fabrication programmable faultcoverage
(FC) and fault-type fault-tolerance method is
provided by the proposed approach of utilizing on-chip builtin
self-test (BIST) resources. These BIST resources are
expected to be already present on VLSI chips because they
are becoming standard in the production environment. The
proposed approach, in addition to its various other
advantages mentioned in section 4, reduces production cost
while leaving the trade-off analysis of maximizing FC and
minimizing performance overhead to be programmable until
post-fabrication.



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