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Cache memory Simulator

Over the past few years, the speed of microprocessors has increased faster than the speed of semiconductor memories. The effective speed of memory can be increased by using a small amount of high-speed cache memory to hold frequently accessed data and instructions. The purpose of this project is to create a cache memory simulator in order to analyze the effect of changing a cache's parameters (size, organization, line size). Ideally, the simulator would be written as a Java applet.



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