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Assertion based verification using HDVL

Abstract
Over the past several years verification of large
designs are becoming more and more complex – both
in terms of the maintaining the code size and in
keeping parity between the specification written in
English; design written in HDL (typically Verilog /
VHDL) and the verification models written in HDL or
some proprietary verification language. To alleviate
this problem, Accellera has come up with the proposal
for standardizing an HDVL – a single language that
caters to all the needs for Design (as an HDL) as well
as Verification (as an HVL – Hardware Verification
Language). SystemVerilog [6] standard where the user
can model and verify the correctness of the designs
using a unified language whose syntax and semantics
is already proven and tested in the industry is being
projected as a candidate HDVL. SystemVerilog is a set
of major enhancements to the Verilog 2001[1]
standard and these enhancements are taken from
existing industry standard languages and paradigms
including Superlog [3], PSL-Sugar [4], OVA [8] and
OVL [7]. In this paper we present an overview of the
Assertion based Verification methodology in general
and explain, with suitable examples, how can one
benefit from using an HDVL for the combined purpose
of design as well as verification. It attempts to set the
right expectations for an engineer from an HDVL and
also illustrates the power of the new paradigm.
1. Introduction
Normally the designers and the verification
engineers use HDLs like Verilog not only for the
design purpose but also for the functional verification
of the designs. To achieve effective functional
verification, large testbenches are written using the
Verilog simulation controls with tool specific
"comment based directives" and the monitors or
checkers are placed in Designs, testbenches as well as
in the simulator tools. But with this approach, the
testing is limited to an ad-hoc basis that finds out only
the visible bugs, and does not check the correctness of
the design. Consequently, the detection of bugs is often
possible only at a later stage of the design flow.
Alternates for the above methodology have been
sought in terms of formal verification primarily
through equivalence checking. This also has capacity
limitations for handling large and complex design both
in terms of memory as well as time requirements.
Recently, assertion based functional verification
methodology has emerged as a new paradigm where
the design / verification engineers can accurately
specify what is to be tested and verified in the form of
well defined temporal language expressions. These are
more abstract than what designers used earlier and can
be directly mapped from the functional specification of
the design. The assertion based technology not only
provides a formal language to the verification
engineer, but also provides the flexibility of reusing
the vendor's verification models (commonly called,
Verification IP) to validate the vendor's design
components as used as a part of the design. The model
checker tools are used to mathematically prove or
disprove the assertions generated from the functional
specification of the design.
Synopsys's OpenVera™ Assertions (OVA) [8] and
IBM's Sugar [9] are examples of such assertion based
languages that have been used in the industry for a
while to create the verification models. Though use of
such languages have aided verification to a certain
extent, being proprietary (and separate from the design
language) they have added to the costs of learning and
working with new languages. Also, the use of different
languages for modeling and verification reduces the
simulator performance besides creating communication
gaps between the design and the verification engineers.
Accellera, the unified body of Open Verilog
International and VHDL International, has proposed to
bridge this gap through the introduction of an HDVL –
a Hardware Description & Verification Language –
that can serve the dual purpose of design as well as the
Proceedings of the 17th International Conference on VLSI Design (VLSID’04)
1063-9667/04 $ 20.00 © 2004 IEEE
functional assertive specification of the design. This
new language, called SystemVerilog, is an effort to
create a paradigm for assertion-based designs with the
help of the building blocks that are already well tested
and are used in the industry. This is an enhancement
over the Verilog 2001 Standard [1] including the
donations mainly from the following well-known
languages:



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