Projects

Design & Verification of the Amba 3 AHB-Lite Protocol

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Project Owner : leelamohan
Created Date : Tue, 12/04/2011 - 18:48
Project Description :

AMBA AHB- Lite addresses the requirements of high-performance synthesizable designs. It is a bus interface that supports a single bus master and provides high-bandwidth operation. AHB-Lite implements the features required for high-performance, high clock frequency systems including:

 

• burst transfers

• Single-clock edge operation

• Non-tristate implementation

• Wide data bus configurations, 64, 128, 256, 512, and 1024 bits.

 

The most common AHB-Lite slaves are internal memory devices, external memory interfaces, and high bandwidth peripherals. Although low-bandwidth peripherals can be included as AHB-Lite slaves, for system performance reasons they typically reside on the AMBA Advanced Peripheral Bus (APB). Bridging between this higher level of bus and APB is done using a AHB-Lite slave, known as an APB bridge. Figure 1-1 shows a single master AHB-Lite system design with one AHB-Lite master and three AHB-Lite slaves. The bus interconnect logic consists of one address decoder and a slave-to-master multiplexor. The decoder monitors the address from the master so

that the appropriate slave is selected and the multiplexor routes the corresponding slave output data back to the master.

 

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The main component types of an AHB-Lite system are described in:

• Master

• Slave

• Decoder

• Multiplexor

 

 

Master

 

   An AHB – Lite Master provides address and control information to intiate read and write operations . the figure 1-2 shows AHB Lite master interface.

 

 

 

In this project the design and verifiaction of MASTER of AMBA3 AHB Lite Protocol is addressed using System Verilog.

 

 

Tools Used:  QUESTA, RIVERA (MENTOR GRAPHICS)

 

Language: System Verilog.

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