what is SIC machine architecture?

Answer1

Simplified Instructional Computer (SIC)

SIC is a hypothetical computer that has been carefully designed to include the hardware features most often found on real machines, while avoiding unusual or irrelevant complexities.
    
     Two version of SIC:
            (i).  Standard model
            (ii).  XE version

      SIC Machine Architecture:
            Memory
(i)   Memory consists of 8-bit bytes
(ii)  Any 3 consecutive bytes form a word (24 bits)
(iii) Total of 32768 (215) bytes in the computer memory

Registers
(i)   Five registers
(ii)  Each register is 24 bits in length

Mnemonic

Number

Special use

       A

     0

Accumulator, used for arithmetic
operations

       X

     1

Index register, used for addressing

       L

     2

Linkage register, JSUB

      PC

     8

Program counter

      SW

     9

Status word, including CC

           

   Data Formats

    1. Integers are stored as 24-bit binary number
    2. 2’s complement representation for negative values
    3. Characters are stored using 8-bit ASCII codes
    4. No floating-point hardware on the standard version of SIC

   Instruction Formats

  opcode (8) 

  X   

  address (15)

 

   

Addressing modes:
          


Mode

Indication 

Target address calculation

Direct

   x = 0

 TA = address

Indirect

   x = 1

 TA = address + (X)

             
      
Instruction Set
(i)  Load and store registers

      1. LDA, LDX, STA, STX, etc.

(ii)  Integer arithmetic operations
                 ·  ADD, SUB, MUL, DIV
                             ·  All arithmetic operations involve register A and a word in memory,
                                with the result being left in the register.                                                                                                    
(iii)  Comparison: COMP
              Comp compares the value in register A and a word in memory.
              This instruction sets a condition code CC to indicate the result.
(iv)  Conditional jump instructions
               JLT, JEQ, JGT.
              These instructions test the setting of CC and jump accordingly.
(v)  Subroutine linkage
              JSUB, RSUB
                          ·  JSUB  jumps to the subroutine, placing the return address in
                             register  L
                          ·  RSUB  returns by jumping to the address contained in
                             register  L
 
     Input and Output
         ·  Input and output are performed by transferring 1 byte at a time to or from the
     rightmost 8 bits of registers A.
         ·  The test device (TD) instruction tests whether the addressed device is ready
     to send or receive a byte of data.
         ·  Read Data (RD)
         ·  Write Data (WD)


Answered by: siva85     On: 30-Apr-2011


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